Serial concatenation of interleaved convolutional codes forming turbo-like codes

ABSTRACT

A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/165,606, filed Jun. 30, 2008, which is a continuation of U.S.application Ser. No. 11/542,950, filed Oct. 3, 2006, now U.S. Pat. No.7,421,032, which is a continuation of U.S. application Ser. No.09/861,102, filed May 18, 2001, now U.S. Pat. No. 7,116,710, whichclaims the priority of U.S. Provisional Application Ser. No. 60/205,095,filed May 18, 2000, and is a continuation-in-part of U.S. applicationSer. No. 09/922,852, filed Aug. 18, 2000, now U.S. Pat. No. 7,089,477.The disclosures of the prior applications are considered part of (andare incorporated by reference in) the disclosure of this application.

GOVERNMENT LICENSE RIGHTS

The U.S. Government has a paid-up license in this invention and theright in limited circumstances to require the patent owner to licenseothers on reasonable terms as provided for by the terms of Grant No.CCR-9804793 awarded by the National Science Foundation.

BACKGROUND

Properties of a channel affect the amount of data that can be handled bythe channel. The so-called “Shannon limit” defines the theoretical limitof the amount of data that a channel can carry.

Different techniques have been used to increase the data rate that canbe handled by a channel. “Near Shannon Limit Error-Correcting Coding andDecoding: Turbo Codes,” by Berrou et al. ICC, pp 1064-1070, (1993),described a new “turbo code” technique that has revolutionized the fieldof error correcting codes. Turbo codes have sufficient randomness toallow reliable communication over the channel at a high data rate nearcapacity. However, they still retain sufficient structure to allowpractical encoding and decoding algorithms. Still, the technique forencoding and decoding turbo codes can be relatively complex.

A standard turbo coder 100 is shown in FIG. 1. A block of k informationbits is input directly to a first coder 102. A k bit interleaver 106also receives the k bits and interleaves them prior to applying them toa second coder 104. The second coder produces an output that has morebits than its input, that is, it is a coder with rate that is lessthan 1. The coders 102, 104 are typically recursive convolutionalcoders.

Three different items are sent over the channel 150: the original kbits, first encoded bits 110, and second encoded bits 112. At thedecoding end, two decoders are used: a first constituent decoder 160 anda second constituent decoder 162. Each receives both the original kbits, and one of the encoded portions 110, 112. Each decoder sendslikelihood estimates of the decoded bits to the other decoders. Theestimates are used to decode the uncoded information bits as corruptedby the noisy channel.

SUMMARY

A coding system according to an embodiment is configured to receive aportion of a signal to be encoded, for example, a data block including afixed number of bits. The coding system includes an outer coder, whichrepeats and scrambles bits in the data block. The data block isapportioned into two or more sub-blocks, and bits in differentsub-blocks are repeated a different number of times according to aselected degree profile. The outer coder may include a repeater with avariable rate and an interleaver. Alternatively, the outer coder may bea low-density generator matrix (LDGM) coder.

The repeated and scrambled bits are input to an inner coder that has arate substantially close to one. The inner coder may include one or moreaccumulators that perform recursive modulo two addition operations onthe input bit stream.

The encoded data output from the inner coder may be transmitted on achannel and decoded in linear time at a destination using iterativedecoding techniques. The decoding techniques may be based on a Tannergraph representation of the code.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a prior “turbo code” system.

FIG. 2 is a schematic diagram of a coder according to an embodiment.

FIG. 3 is a Tanner graph for an irregular repeat and accumulate (IRA)coder.

FIG. 4 is a schematic diagram of an IRA coder according to anembodiment.

FIG. 5A illustrates a message from a variable node to a check node onthe Tanner graph of FIG. 3.

FIG. 5B illustrates a message from a check node to a variable node onthe Tanner graph of FIG. 3.

FIG. 6 is a schematic diagram of a coder according to an alternateembodiment.

FIG. 7 is a schematic diagram of a coder according to another alternateembodiment.

DETAILED DESCRIPTION

FIG. 2 illustrates a coder 200 according to an embodiment. The coder 200may include an outer coder 202, an interleaver 204, and inner coder 206.The coder may be used to format blocks of data for transmission,introducing redundancy into the stream of data to protect the data fromloss due to transmission errors. The encoded data may then be decoded ata destination in linear time at rates that may approach the channelcapacity.

The outer coder 202 receives the uncoded data. The data may bepartitioned into blocks of fixed size, say k bits. The outer coder maybe an (n,k) binary linear block coder, where n>k. The coder accepts asinput a block u of k data bits and produces an output block v of n databits. The mathematical relationship between u and v is v=T₀u, where T₀is an n×k matrix, and the rate of the coder is k/n.

The rate of the coder may be irregular, that is, the value of T₀ is notconstant, and may differ for sub-blocks of bits in the data block. In anembodiment, the outer coder 202 is a repeater that repeats the k bits ina block a number of times q to produce a block with n bits, where n=qk.Since the repeater has an irregular output, different bits in the blockmay be repeated a different number of times. For example, a fraction ofthe bits in the block may be repeated two times, a fraction of bits maybe repeated three times, and the remainder of bits may be repeated fourtimes. These fractions define a degree sequence, or degree profile, ofthe code.

The inner coder 206 may be a linear rate-1 coder, which means that then-bit output block x can be written as x=T_(I)w, where T_(I) is anonsingular n×n matrix. The inner coder 210 can have a rate that isclose to 1, e.g., within 50%, more preferably 10% and perhaps even morepreferably within 1% of 1.

In an embodiment, the inner coder 206 is an accumulator, which producesoutputs that are the modulo two (mod-2) partial sums of its inputs. Theaccumulator may be a truncated rate-1 recursive convolutional coder withthe transfer function 1/(1+D). Such an accumulator may be considered ablock coder whose input block [x₁, . . . , x_(n)] and output block [y₁,. . . , y_(n)] are related by the formula

y₁=x₁

y₂=x₁⊕x₂

y₃=x₁⊕x₂⊕x₃

∩

y_(n)=x₁⊕x₂⊕x₃⊕ . . . ⊕x_(n)

where “⊕” denotes mod-2, or exclusive-OR (XOR), addition. An advantageof this system is that only mod-2 addition is necessary for theaccumulator. The accumulator may be embodied using only XOR gates, whichmay simplify the design.

The bits output from the outer coder 202 are scrambled before they areinput to the inner coder 206. This scrambling may be performed by theinterleaver 204, which performs a pseudo-random permutation of an inputblock v, yielding an output block w having the same length as v.

The serial concatenation of the interleaved irregular repeat code andthe accumulate code produces an irregular repeat and accumulate (IRA)code. An IRA code is a linear code, and as such, may be represented as aset of parity checks. The set of parity checks may be represented in abipartite graph, called the Tanner graph, of the code. FIG. 3 shows aTanner graph 300 of an IRA code with parameters (f₁, f_(j); a), wheref_(i)≧0, Σ_(i)f_(i)=1 and “a” is a positive integer. The Tanner graphincludes two kinds of nodes: variable nodes (open circles) and checknodes (filled circles). There are k variable nodes 302 on the left,called information nodes. There are r variable nodes 306 on the right,called parity nodes. There are r=(kΣ_(i)if_(i))/a check nodes 304connected between the information nodes and the parity nodes. Eachinformation node 302 is connected to a number of check nodes 304. Thefraction of information nodes connected to exactly i check nodes isf_(i). For example, in the Tanner graph 300, each of the f₂ informationnodes are connected to two check nodes, corresponding to a repeat ofq=2, and each of the f₃ information nodes are connected to three checknodes, corresponding to q=3.

Each check node 304 is connected to exactly “a” information nodes 302.In FIG. 3, a=3. These connections can be made in many ways, as indicatedby the arbitrary permutation of the ra edges joining information nodes302 and check nodes 304 in permutation block 310. These connectionscorrespond to the scrambling performed by the interleaver 204.

In an alternate embodiment, the outer coder 202 may be a low-densitygenerator matrix (LDGM) coder that performs an irregular repeat of the kbits in the block, as shown in FIG. 4. As the name implies, an LDGM codehas a sparse (low-density) generator matrix. The IRA code produced bythe coder 400 is a serial concatenation of the LDGM code and theaccumulator code. The interleaver 204 in FIG. 2 may be excluded due tothe randomness already present in the structure of the LDGM code.

If the permutation performed in permutation block 310 is fixed, theTanner graph represents a binary linear block code with k informationbits (u_(i), . . . , u_(k)) and r parity bits (x₁, . . . , x_(r)), asfollows. Each of the information bits is associated with one of theinformation nodes 302, and each of the parity bits is associated withone of the parity nodes 306. The value of a parity bit is determineduniquely by the condition that the mod-2 sum of the values of thevariable nodes connected to each of the check nodes 304 is zero. To seethis, set x₀=0. Then if the values of the bits on the ra edges comingout the permutation box are (v₁, . . . , v_(ra)), then we have therecursive formula for j=1, 2, . . . , r. This is in effect the encodingalgorithm.

Two types of IRA codes are represented in FIG. 3, a nonsystematicversion and

$x_{j} = {x_{j - 1} + {\sum\limits_{i = 1}^{a}v_{{{({j - 1})}a} + i}}}$

a systematic version. The nonsystematic version is an (r,k) code, inwhich the codeword corresponding to the information bits (u₁, . . . ,u_(k)) is (x₁, . . . , x_(r)). The systematic version is a (k+r, k)code, in which the codeword is (u₁, . . . , u_(k); x₁, . . . , x_(r)).

$R_{nsys} = \frac{a}{\sum\limits_{i}{if}_{i}}$

The rate of the nonsystematic code is

The rate of the systematic code is

$R_{sys} = \frac{a}{a + {\sum\limits_{i}{if}_{i}}}$

For example, regular repeat and accumulate (RA) codes can be considerednonsystematic IRA codes with a=1 and exactly one f_(i) equal to 1, sayf_(q)=1, and the rest zero, in which case R_(nsys) simplifies to R=1/q.

The IRA code may be represented using an alternate notation. Let λ_(i)be the fraction of edges between the information nodes 302 and the checknodes 304 that are

$f_{i} = \frac{\lambda_{i}/i}{\sum\limits_{j}{\lambda_{j}/j}}$

adjacent to an information node of degree i, and let p, be the fractionof such edges that are adjacent to a check node of degree i+2 (i.e., onethat is adjacent to i information nodes). These edge fractions may beused to represent the IRA code rather than the corresponding nodefractions. Define λ(x)=Σ_(i)λ_(i)x^(i-1) and ρ(x)=Σ_(i)ρ_(i)x^(i-1) tobe the generating functions of these sequences. The pair (λ, ρ) iscalled a degree distribution. For L(x)=Σ_(i)f_(i)x_(i),

The rate of the systematic IRA code given by the degree distribution isgiven by

L(x) = ∫₀^(x)λ(t)t/∫₀¹λ(t)t${Rate} = \left( {1 + \frac{\sum\limits_{j}{\rho_{j}/j}}{\sum\limits_{j}{\lambda_{j}/j}}} \right)^{- 1}$

“Belief propagation” on the Tanner Graph realization may be used todecode IRA codes. Roughly speaking, the belief propagation decodingtechnique allows the messages passed on an edge to represent posteriordensities on the bit associated with the variable node. A probabilitydensity on a bit is a pair of non-negative real numbers p(0), p(1)satisfying p(0)+p(1)=1, where p(0) denotes the probability of the bitbeing 0, p(1) the probability of it being 1. Such a pair can berepresented by its log likelihood ratio, m=log(p(0)/p(1)). The outgoingmessage from a variable node u to a check node v represents informationabout u, and a message from a check node u to a variable node vrepresents information about u, as shown in FIGS. 5A and 5B,respectively.

The outgoing message from a node u to a node v depends on the incomingmessages from all neighbors w of u except v. If u is a variable messagenode, this outgoing message is

${m\left( {u->v} \right)} = {{\sum\limits_{w \neq v}{m\left( {w->u} \right)}} + {m_{0}(u)}}$

where m₀(u) is the log-likelihood message associated with u. If u is acheck node, the

${\tanh \; \frac{m\left( {u->v} \right)}{2}} = {\prod\limits_{w \neq v}{\tanh \; \frac{m\left( {w->u} \right)}{2}}}$

corresponding formula is

Before decoding, the messages m(w→u) and m(u→v) are initialized to bezero, and m₀(u) is initialized to be the log-likelihood ratio based onthe channel received information. If the channel is memoryless, i.e.,each channel output only relies on its input, and y is the output of thechannel code bit u, then m₀(u)=log(p(u=O|y)/p(u=1|y)). After thisinitialization, the decoding process may run in a fully parallel andlocal manner. In each iteration, every variable/check node receivesmessages from its neighbors, and sends back updated messages. Decodingis terminated after a fixed number of iterations or detecting that allthe constraints are satisfied. Upon termination, the decoder outputs adecoded sequence based on the messages m(u)=Σw_(m)(w→u).

Thus, on various channels, iterative decoding only differs in theinitial messages m₀(u). For example, consider three memoryless channelmodels: a binary erasure channel (BEC); a binary symmetric channel(BSC); and an additive white Gaussian noise (AGWN) channel.

In the BEC, there are two inputs and three outputs. When 0 istransmitted, the receiver can receive either 0 or an erasure E. Anerasure E output means that the receiver does not know how to demodulatethe output. Similarly, when 1 is transmitted, the receiver can receiveeither 1 or E. Thus, for the BEC, yε{0, E, 1}, and

In the BSC, there are two possible inputs (0,1) and two possible outputs(0, 1).

${m_{0}(u)} = \left\{ \begin{matrix}{+ \infty} & {if} & {y = 0} \\0 & {if} & {y = E} \\{- \infty} & {if} & {y = 1}\end{matrix} \right.$

The BSC is characterized by a set of conditional probabilities relatingall possible outputs to possible inputs. Thus, for the BSC yε{0, 1}, and

${m_{0}(u)} = \left\{ \begin{matrix}{\log \; \frac{1 - p}{p}} & {if} & {y = 0} \\{{- \log}\; \frac{1 - p}{p}} & {if} & {y = 1}\end{matrix} \right.$

In the AWGN, the discrete-time input symbols X take their values in afinite alphabet while channel output symbols Y can take any values alongthe real line. There is assumed to be no distortion or other effectsother than the addition of white Gaussian noise. In an AWGN with aBinary Phase Shift Keying (BPSK) signaling which maps 0 to the symbolwith amplitude √{square root over (Es)} and 1 to the symbol withamplitude −√{square root over (Es)}, output y εR, then

where N₀/2 is the noise power spectral density.

The selection of a degree profile for use in a particular transmissionchannel is a design parameter, which may be affected by variousattributes of the channel. The criteria for selecting a particulardegree profile may include, for example, the type of channel and thedata rate on the channel. For example, Table 1 shows degree profilesthat have been found to produce good results for an AWGN channel model.

TABLE 1 a 2 3 4 λ2  0.139025 0.078194 0.054485 λ3  0.2221555 0.1280850.104315 λ5  0.160813 λ6  0.638820 0.036178 0.126755 λ10 0.229816 λ110.016484 λ12 0.108828 λ13 0.487902 λ14 λ16 λ27 0.450302 λ28 0.017842Rate 0.333364 0.333223 0.333218 σGA 1.1840 1.2415 1.2615 σ* 1.19811.2607 1.2780 (Eb/N0) * (dB) 0.190 −0.250 −0.371 S.L. (dB) −0.4953−0.4958 −0.4958

Table 1 shows degree profiles yielding codes of rate approximately ⅓ forthe AWGN channel and with a=2, 3, 4. For each sequence, the Gaussianapproximation noise threshold, the actual sum-product decoding thresholdand the corresponding energy per bit (E_(b))-noise power (N₀) ratio indB are given. Also listed is the Shannon limit (S.L.).

As the parameter “a” is increased, the performance improves. Forexample, for a=4, the best code found has an iterative decodingthreshold of E_(b)/N₀=−0.371 dB, which is only 0.12 dB above the Shannonlimit.

The accumulator component of the coder may be replaced by a “doubleaccumulator” 600 as shown in FIG. 6. The double accumulator can beviewed as a truncated rate 1 convolutional coder with transfer function1/(1+D+D²).

Alternatively, a pair of accumulators may be the added, as shown in FIG.7. There are three component codes: the “outer” code 700, the “middle”code 702, and the “inner” code 704. The outer code is an irregularrepetition code, and the middle and inner codes are both accumulators.

IRA codes may be implemented in a variety of channels, includingmemoryless channels, such as the BEC, BSC, and AWGN, as well as channelshaving non-binary input, non-symmetric and fading channels, and/orchannels with memory.

A number of embodiments have been described. Nevertheless, it will beunderstood that various modifications may be made without departing fromthe spirit and scope of the invention. Accordingly, other embodimentsare within the scope of the following claims.

1. An apparatus for performing encoding operations, the apparatuscomprising: a first set of memory locations to store information bits; asecond set of memory locations to store parity bits; a permutationmodule to read a bit from the first set of memory locations and combinethe read bit to a bit in the second set of memory locations based on acorresponding index of the first set of memory locations and acorresponding index of the second set of memory locations; and anaccumulator to perform accumulation operations on the bits stored in thesecond set of memory locations, wherein a total number of indices of thefirst set of memory locations represents a variable number.
 2. Theapparatus of claim 1, wherein the permutation module is configured toperform the combine operation to include performing mod-2 orexclusive-OR sum.
 3. The apparatus of claim 2, wherein the permutationmodule is configured to perform the combining operation to furtherinclude writing the sum to the second set of memory locations based on acorresponding index.
 4. The apparatus of claim 1, wherein theaccumulator is configured to perform the accumulation operation toinclude a mod-2 or exclusive-OR sum of the bit stored in a prior indexto a bit stored in a current index based on a corresponding index of thesecond set of memory locations.
 5. The apparatus of claim 4, wherein theaccumulator is configured to perform the accumulation operation to atleast 2 consecutive indices of the second set of memory locations. 6.The apparatus of claim 1, wherein the permutation module furthercomprises a permutation information module to generate pairs of an indexof the first set of memory locations and an index of the second set ofmemory locations.
 7. The apparatus of claim 6, wherein at least oneindex of the second set of memory locations is used twice.
 8. A methodof performing encoding operations, the method comprising: receiving asequence of information bits from a first set of memory locations;performing an encoding operation using the received sequence ofinformation bits as an input, said encoding operation comprising:reading a bit from the received sequence of information bits, andcombining the read bit to a bit in a second set of memory locationsbased on a corresponding index of the first set of memory locations forthe received sequence of information bits and a corresponding index ofthe second set of memory locations; and accumulating the bits in thesecond set of memory locations, wherein a total number of indices of thefirst set of memory locations corresponding to the received sequence ofinformation bits is a variable number.
 9. The method of claim 8, whereinperforming the combine operation comprises performing mod-2 orexclusive-OR sum.
 10. The method of claim 9, wherein performing thecombine operation comprises writing the sum to the second set of memorylocations based on a corresponding index.
 11. The method of claim 8,wherein performing the accumulation operation comprises performing amod-2 or exclusive-OR sum of the bit stored in a prior index to a bitstored in a current index based on a corresponding index of the secondset of memory locations.
 12. The method of claim 8, wherein theaccumulation operation is performed to at least 2 consecutive indices ofthe second set of memory locations.
 13. The method of claim 8, whereinthe combining operation comprises generating pairs of an index of thefirst set of memory locations and an index of the second set of memorylocations.
 14. The method of claim 13, wherein at least one index of thesecond set of memory locations is used twice.